1. Field of the Invention
The present invention relates to semiconductor packaging. More particularly, the present invention relates to a semiconductor package with multiple coplanar interposers.
2. Description of the Prior Art
Integrated circuit (IC) chips are typically assembled into packages that are soldered to a printed circuit board (PCB). Each integrated circuit chip may be connected to a substrate of the package with a number of solder bumps in a process commonly referred to as controlled collapsed chip connection (C4).
As known in the art, an interposer substrate such as a silicon interposer with through silicon vias (TSVs) is usually used in semiconductor packaging to “fan out” the contacts of the integrated circuit chips. As more chips are assembled in one package, the size and the surface area of the interposer substrate are also increased.
For example, for mounting a processor chip such as a Graphics Processing Unit (GPU) and several memory chips such as Graphics Double Data Rate (GDDR) chips or High-Bandwidth Memory (HBM) chips, a large-size interposer substrate having a surface area of up to 33 mm×28 mm is typically required.
However, the size of silicon interposers from the leading foundries is currently limited to 26 mm×32 mm. To fabricate the large-size silicon interposers, yields can decrease thereby increasing the cost of producing the semiconductor packages.
Further, large-size interposer substrates are prone to significant warpage when used as part of a semiconductor package, particularly during the reflow process. Warpage of the interposer substrate during fabrication of a semiconductor package can reduce yield and result in poor package reliability, both of which are highly undesirable.